This is the eighth post of the series of the sequence detectors. You can find my previous post here: sequence 11010, sequence 1101, sequence 1010, sequence 1011, sequence 1001, sequence 101, and sequence 110. We are going to cover all four possible scenarios below:
1) Moore Machine (Non-Overlapping)
module sd10011_moore(input bit clk,
input logic reset,
input logic din,
output logic dout);
typedef enum logic [2:0] {S0, S1, S2, S3, S4, S5} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(~din)
state <= S2;
end
S2: begin
dout <= 1'b0;
if(~din)
state <= S3;
else
state <= S1;
end
S3: begin
dout <= 1'b0;
if(din)
state <= S4;
else
state <= S0;
end
S4: begin
dout <= 1'b0;
if(din)
state <= S5;
else
state <= S2;
end
S5: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S0;
end
endcase
end
end
endmodule
input logic reset,
input logic din,
output logic dout);
typedef enum logic [2:0] {S0, S1, S2, S3, S4, S5} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(~din)
state <= S2;
end
S2: begin
dout <= 1'b0;
if(~din)
state <= S3;
else
state <= S1;
end
S3: begin
dout <= 1'b0;
if(din)
state <= S4;
else
state <= S0;
end
S4: begin
dout <= 1'b0;
if(din)
state <= S5;
else
state <= S2;
end
S5: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S0;
end
endcase
end
end
endmodule
2) Mealy Machine (Non-Overlapping)
module sd10011_mealy(input bit clk,
input logic reset,
input logic din,
output logic dout);
typedef enum logic [2:0] {S0, S1, S2, S3, S4} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(~din) begin
state <= S2;
dout <=1'b0;
end
else begin
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S3;
dout <=1'b0;
end
else begin
state <= S1;
dout <=1'b0;
end
end
S3: begin
if(din) begin
state <= S4;
dout <=1'b0;
end
else begin
state <= S0;
dout <=1'b0;
end
end
S4: begin
if(din) begin
state <= S0;
dout <=1'b1;
end
else begin
state <= S2;
dout <=1'b0;
end
end
endcase
end
end
endmodule
input logic reset,
input logic din,
output logic dout);
typedef enum logic [2:0] {S0, S1, S2, S3, S4} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(~din) begin
state <= S2;
dout <=1'b0;
end
else begin
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S3;
dout <=1'b0;
end
else begin
state <= S1;
dout <=1'b0;
end
end
S3: begin
if(din) begin
state <= S4;
dout <=1'b0;
end
else begin
state <= S0;
dout <=1'b0;
end
end
S4: begin
if(din) begin
state <= S0;
dout <=1'b1;
end
else begin
state <= S2;
dout <=1'b0;
end
end
endcase
end
end
endmodule
3) Moore Machine (Overlapping)
module sd10011_moore_over(input bit clk,
input logic reset,
input logic din,
output logic dout);
typedef enum logic [2:0] {S0, S1, S2, S3, S4, S5} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(~din)
state <= S2;
end
S2: begin
dout <= 1'b0;
if(~din)
state <= S3;
else
state <= S1;
end
S3: begin
dout <= 1'b0;
if(din)
state <= S4;
else
state <= S0;
end
S4: begin
dout <= 1'b0;
if(din)
state <= S5;
else
state <= S2;
end
S5: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S2;
end
endcase
end
end
endmodule
input logic reset,
input logic din,
output logic dout);
typedef enum logic [2:0] {S0, S1, S2, S3, S4, S5} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(~din)
state <= S2;
end
S2: begin
dout <= 1'b0;
if(~din)
state <= S3;
else
state <= S1;
end
S3: begin
dout <= 1'b0;
if(din)
state <= S4;
else
state <= S0;
end
S4: begin
dout <= 1'b0;
if(din)
state <= S5;
else
state <= S2;
end
S5: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S2;
end
endcase
end
end
endmodule
4) Mealy Machine (Overlapping)
module sd10011_mealy_over(input bit clk,
input logic reset,
input logic din,
output logic dout);
typedef enum logic [2:0] {S0, S1, S2, S3, S4} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(~din) begin
state <= S2;
dout <=1'b0;
end
else begin
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S3;
dout <=1'b0;
end
else begin
state <= S1;
dout <=1'b0;
end
end
S3: begin
if(din) begin
state <= S4;
dout <=1'b0;
end
else begin
state <= S0;
dout <=1'b0;
end
end
S4: begin
if(din) begin
state <= S1;
dout <=1'b1;
end
else begin
state <= S2;
dout <=1'b0;
end
end
endcase
end
end
endmodule
input logic reset,
input logic din,
output logic dout);
typedef enum logic [2:0] {S0, S1, S2, S3, S4} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(~din) begin
state <= S2;
dout <=1'b0;
end
else begin
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S3;
dout <=1'b0;
end
else begin
state <= S1;
dout <=1'b0;
end
end
S3: begin
if(din) begin
state <= S4;
dout <=1'b0;
end
else begin
state <= S0;
dout <=1'b0;
end
end
S4: begin
if(din) begin
state <= S1;
dout <=1'b1;
end
else begin
state <= S2;
dout <=1'b0;
end
end
endcase
end
end
endmodule
That’s all for sequence detector 10011. Leave me a comment if you have any questions.