# Solving Knight’s Tour Problem Using SystemVerilog Constraints

Hi, I was asked by one of my readers to solve this problem using SystemVerilog. It definitely took me some time to figure out how I would like to model the chessboard. So today I would like to share my solution here. First, let’s take a look at the definition of this problem. According to… Continue reading Solving Knight’s Tour Problem Using SystemVerilog Constraints

# 3 Ways to Generate an Ascending Array Using SystemVerilog Constraints

Hi, I would like to describe three methods to generate an ascending array using SystemVerilog constraints. You can generate a descending array via a similar approach. Using array sort method One way to do it is to generate a random array with unique values. In the post_randomize() function, we can sort the array using sort()… Continue reading 3 Ways to Generate an Ascending Array Using SystemVerilog Constraints

# Sequence Detector 11011 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)

Hi all, this is the ninth and the last post of the sequence detectors design series for now. I might add more contents related to this topic in the future. However, these are all I plan to cover currently. You can find my previous posts here: Sequence 10011 , sequence 11010, sequence 1101, sequence 1010,… Continue reading Sequence Detector 11011 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)

# A Slightly Better Way to Implement Tic-Tac-Toe Using SystemVerilog Constraints

In the previous post, I talked about a rudimentary way that I think of to implement Tic-Tac-Toe in SystemVerilog. As promised, I am going to write about how to improve on the grid modeling and achieve a slightly more efficient solution. For this solution, we are going to look at the grid in a more… Continue reading A Slightly Better Way to Implement Tic-Tac-Toe Using SystemVerilog Constraints

# A Rudimentary Way to Implement Tic-Tac-Toe Using SystemVerilog Constraints

You can do lots of fun things using SystemVerilog Constraint. There are famous Einstein house puzzle, Eight queen puzzle, and many more can be solved using SystemVerilog constraints. Today I would like to talk about how to implement Tic-Tac-Toe result using SystemVerilog constraints. I call this a rudimentary approach is because I didn’t take code… Continue reading A Rudimentary Way to Implement Tic-Tac-Toe Using SystemVerilog Constraints

# Sequence Detector 10011 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)

This is the eighth post of the series of the sequence detectors. You can find my previous post here: sequence 11010, sequence 1101, sequence 1010, sequence 1011, sequence 1001, sequence 101, and sequence 110. We are going to cover all four possible scenarios below: 1) Moore Machine (Non-Overlapping) module sd10011_moore(input bit clk,      … Continue reading Sequence Detector 10011 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)

# 3 Ways to Generate One Hot Vector Using SystemVerilog Constraints

One hot decoding and encoding are widely used in RTL programming. It is essential to generate one hot vector sometimes using SystemVerilog constraints. There are 2 built-in functions we can use. Also, we can use bit manipulation to achieve the same result as well. I am going to talk about how to generate one hot… Continue reading 3 Ways to Generate One Hot Vector Using SystemVerilog Constraints

# Implementing Randc Function in SystemVerilog without Actually Using Randc Variables

Hi, I would like to take a peek at randc variables today, and then talk about implementing it in a way with only rand variables.   For starter, let’s take a look at the definition of randc modifier. It’s defined in RFM 18.4.2. Variables declared with the randc keyword are random-cyclic variables that cycle through… Continue reading Implementing Randc Function in SystemVerilog without Actually Using Randc Variables

# 4 Ways to Randomize the Number of Ones in a Variable Using SystemVerilog Constraints

Hi, today I am going to write about how to write different constraints in SystemVerilog to achieve the same goal, to randomize the number of ones in a variable.   Using built-in \$countones function This is the most intuitive way for me. You can simply just call the built-in function, and SystemVerilog will take care… Continue reading 4 Ways to Randomize the Number of Ones in a Variable Using SystemVerilog Constraints

# Generate a Valid Phone Number Using SystemVerilog Constraints

Hi, today I would like to talk about how to use SystemVerilog constraints to generate some valid phone numbers. So the valid phone number formats are listed below: Front Desk Operator Number:0 Emergency Number: 911 Local Phone Number (No Area Code): XXX-XXXX Non-Local Phone Number: 1-XXX-XXX-XXXX Those four types of phone numbers follow the distribution… Continue reading Generate a Valid Phone Number Using SystemVerilog Constraints