This is the seventh post of the sequence detector design series. Today we are going to take a look at a 5-digit sequence, 10010. The previous posts can be found here: sequence 1101, sequence 1010, sequence 1011, sequence 1001, sequence 101, and sequence 110. We are going to cover all four possible scenarios below: 1)… Continue reading Sequence Detector 10010 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)

Hi, this is the sixth post of the sequence detectors design series. The previous posts can be found here: sequence 1010, sequence 1011, sequence 1001, sequence 101, and sequence 110. I am going to cover both the Moore machine and Mealy machine in overlapping and non-overlapping cases. 1) Moore machine (Non-Overlapping) module sd1101_moore(input bit clk,… Continue reading Sequence Detector 1101 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)

Hi, this post is about how to design and implement a sequence detector to detect 1010. This is the fifth post of the series. The previous posts can be found here: sequence 1011, sequence 1001, sequence 101, and sequence 110. I am going to cover both the Moore machine and Mealy machine in overlapping and… Continue reading Sequence Detector 1010 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)

Hi, this is the fourth post of the series of sequence detectors design. The previous posts can be found here: sequence 1001, sequence 101, and sequence 110. Today we are going to take a look at sequence 1011. For 1011, we also have both overlapping and non-overlapping cases. 1) Moore Machine (Non-Overlapping) module sd1011_moore(input bit… Continue reading Sequence Detector 1011 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)

Hi guys, what I would like to share with you today is how to use SystemVerilog constraints to generate an array with unique elements. There are three ways that I can think of. The first one is to use the uniqueness constraints in SystemVerilog syntax, the other two ways are to use array iterators to… Continue reading 3 Ways to Generate an Array with Unique Elements Using SystemVerilog Constraints

Hi! It has been a while. Darn holiday seasons. I lost all my little productivity in the past two months. It’s time to get some work done. Today I want to talk about how to build a linked list using SystemVerilog. Linked lists are widely used in programming. However, it’s less commonly seen in HDLs… Continue reading 3 Ways to Build a Linked List Using SystemVerilog

Hi, today I’m going to post my thoughts on how to solve the N Queens problem using constraints in SystemVerilog. I am using one particular algorithm to solve it. I believe there must also be other ways to model the chessboard to approach this problem using other constraints. If I have time later, I will… Continue reading Solving the N Queens Problem in SystemVerilog

Hi, this is the third post of the series of sequence detectors design. The previous posts can be found here: sequence 101 and sequence 110. Today we are going to look at sequence 1001. I’m going to do the design in both Moore Machine and Mealy Machine, also consider both overlapping and non-overlapping scenarios. 1)… Continue reading Sequence Detector 1001 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)

Hi, this is the second post of the series of sequence detectors design. You can find my previous post about sequence detector 101 here. Today we are going to look at sequence 110. I’m going to do the design in both Moore machine and Mealy machine. This sequence doesn’t really need to consider overlapping or… Continue reading Sequence Detector 110 (Moore Machine + Mealy Machine)

Hi, I plan to do a series of sequence detectors design. A sequence detector is a sequential circuit that outputs 1 when a particular pattern of bits sequentially arrives at its data input. A sequence detector’s functions are achieved by using a finite state machine. For this post, I’ll share my finite state machine diagrams… Continue reading Sequence Detector 101