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Yue Guo

Design Verification

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      • Four types of 64-bit Adders
      • The Design of a USART
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Design

These are some of ASIC/SoC design projects I’ve done:

  • Implementation and Analysis of Various 64-bit Adders
  • The Design of 5-stage Pipelined MIPS Processor
  • The Design of a Data Scrambler
  • The Design of SoC Bus Arbiter Design
  • The Design of a USART

Recent Posts

  • Solving Knight’s Tour Problem Using SystemVerilog Constraints
  • 3 Ways to Generate an Ascending Array Using SystemVerilog Constraints
  • Sequence Detector 11011 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)
  • A Slightly Better Way to Implement Tic-Tac-Toe Using SystemVerilog Constraints
  • A Rudimentary Way to Implement Tic-Tac-Toe Using SystemVerilog Constraints
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