Hi, this is the second post of the series of sequence detectors design. You can find my previous post about sequence detector 101 here. Today we are going to look at sequence 110. I’m going to do the design in both Moore machine and Mealy machine. This sequence doesn’t really need to consider overlapping or non-overlapping senarios.
1) Moore Machine
module sd110_moore(input bit clk,
input logic reset,
input logic din,
output logic dout);
typedef enum logic [1:0] {S0, S1, S2, S3} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(din)
state <= S2;
else
state <= S0;
end
S2: begin
dout <= 1'b0;
if(~din)
state <= S3;
end
S3: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S0;
end
endcase
end
end
endmodule
input logic reset,
input logic din,
output logic dout);
typedef enum logic [1:0] {S0, S1, S2, S3} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(din)
state <= S2;
else
state <= S0;
end
S2: begin
dout <= 1'b0;
if(~din)
state <= S3;
end
S3: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S0;
end
endcase
end
end
endmodule
2) Mealy Machine
module sd110_mealy(input bit clk,
input logic reset,
input logic din,
output logic dout);
typedef enum logic [1:0] {S0, S1, S2} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(din) begin
state <= S2;
dout <=1'b0;
end
else begin
state <= S0;
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S0;
dout <=1'b1;
end
else begin
dout <=1'b0;
end
end
endcase
end
end
endmodule
input logic reset,
input logic din,
output logic dout);
typedef enum logic [1:0] {S0, S1, S2} state_t;
state_t state;
always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(din) begin
state <= S2;
dout <=1'b0;
end
else begin
state <= S0;
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S0;
dout <=1'b1;
end
else begin
dout <=1'b0;
end
end
endcase
end
end
endmodule
Again, I did some simple testbench checking, and all of them worked. Let me know if you have any questions or I made some silly mistakes.