Sequence Detector 1001 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)

Hi, this is the third post of the series of sequence detectors design. The previous posts can be found here: sequence 101 and sequence 110. Today we are going to look at sequence 1001. I’m going to do the design in both Moore Machine and Mealy Machine, also consider both overlapping and non-overlapping scenarios.

1) Moore Machine (Non-Overlapping)

module sd1001_moore(input bit clk,
input logic reset,
input logic din,
output logic dout);

typedef enum logic [2:0] {S0, S1, S2, S3, S4} state_t;
state_t state;

always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(~din)
state <= S2;
end
S2: begin
dout <= 1'b0;
if(~din)
state <= S3;
else
state <= S1;
end
S3: begin
dout <= 1'b0;
if(din)
state <= S4;
else
state <= S0;
end
S4: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S0;
end
endcase
end
end

endmodule

2) Mealy Machine (Non-Overlapping)

module sd1001_mealy(input bit clk,
input logic reset,
input logic din,
output logic dout);

typedef enum logic [1:0] {S0, S1, S2, S3} state_t;
state_t state;

always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(~din) begin
state <= S2;
dout <=1'b0;
end
else begin
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S3;
dout <=1'b0;
end
else begin
state <= S1;
dout <=1'b0;
end
end
S3: begin
if(din) begin
state <= S0;
dout <=1'b1;
end
else begin
state <= S0;
dout <=1'b0;
end
end
endcase
end
end

endmodule

3) Moore Machine (Overlapping)

module sd1001_moore_over(input bit clk,
input logic reset,
input logic din,
output logic dout);

typedef enum logic [2:0] {S0, S1, S2, S3, S4} state_t;
state_t state;

always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(~din)
state <= S2;
end
S2: begin
dout <= 1'b0;
if(~din)
state <= S3;
else
state <= S1;
end
S3: begin
dout <= 1'b0;
if(din)
state <= S4;
else
state <= S0;
end
S4: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S2;
end
endcase
end
end

endmodule

4) Mealy Machine (Overlapping)

module sd1001_mealy_over(input bit clk,
input logic reset,
input logic din,
output logic dout);

typedef enum logic [1:0] {S0, S1, S2, S3} state_t;
state_t state;

always @(posedge clk or posedge reset) begin
if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(~din) begin
state <= S2;
dout <=1'b0;
end
else begin
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S3;
dout <=1'b0;
end
else begin
state <= S1;
dout <=1'b0;
end
end
S3: begin
if(din) begin
state <= S1;
dout <=1'b1;
end
else begin
state <= S0;
dout <=1'b0;
end
end
endcase
end
end

endmodule

Again, I did some simple testbench checking, and all of them worked. Let me know if you have any questions or I made some silly mistakes.

3 thoughts on “Sequence Detector 1001 (Moore Machine + Mealy Machine + Overlapping/Non-Overlapping)”

1. Qisheng Fu says:

This is one of the Interview problems of Micron. Thank you for your explanation.

1. Yue Guo says:

I am glad that I could help. ðŸ™‚