# 3 Ways to Generate One Hot Vector Using SystemVerilog Constraints

One hot decoding and encoding are widely used in RTL programming. It is essential to generate one hot vector sometimes using SystemVerilog constraints. There are 2 built-in functions we can use. Also, we can use bit manipulation to achieve the same result as well. I am going to talk about how to generate one hot vector in three different ways below:

1. Using built-in \$onehot function
2. The \$onehot function is defined in the RFM 20.9. We have a brief description below:
\$onehot ( expression ) returns true (1’b1) if \$countbits(expression,’1)==1, otherwise it returns false (1’b0).

We can use this in our constraint and make sure the return value of the \$onehot function is 1, which means the vector is one hot.

program p1;

class c1;
rand bit [3:0] a;

constraint c1 {
\$onehot(a) ==1;
}

endclass

c1 c1_h;

initial begin
c1_h = new();

repeat(3) begin
if(c1_h.randomize())
\$display("a is %b", c1_h.a);
end

end

endprogram

3. Using built-in \$countones function
4. The \$countones returns how many set bits there are. For one hot coding, we want to make sure there is only one bit is set. So in the constraint, the return value of \$countones should be set to 1.

program p1;

class c1;
rand bit [3:0] a;

//only one bit is set
constraint c1 {
\$countones(a) ==1;
}

endclass

c1 c1_h;

initial begin
c1_h = new();

repeat(3) begin
if(c1_h.randomize())
\$display("a is %b", c1_h.a);
end
end
endprogram

5. Using bit manipulation
6. This is the more algorithmic method and requires a bit of programming background. One hot vector can also be expressed as an integer which is a power of 2. This is a classic programming question. We just need to make sure a & (a-1) is 0, and a does not equal to 0. This is because a only has one bit is set to high, if we take 1 from a, the bits lower than the set bit become 1 and the original set bit is 0. If we perform bitwise and &, we are going to get 0. So we can just put these requirements in the constraint.

One thing to mention here. Because of SystemVerilog operator precedence, bitwise and & is lower than ==, we have to put a pair of parentheses on the left side of the function, (a & (a-1)) == 0, to guarantee the constraint is solved as we intended.

program p1;

class c1;
rand bit [3:0] a;

//bit manipulation
constraint c1 {
// Attention! You need to use the parentheses on the right of the equation
(a & (a-1)) == 0;
a !=0;
}

endclass

c1 c1_h;

initial begin
c1_h = new();

repeat(3) begin
if(c1_h.randomize())
\$display("a is %b", c1_h.a);
end

end

endprogram

1. RAJESH BHUYAN says: