Nice to meet you

Hi! I’m Yue Guo, an enthusiastic ASIC Design Verification Engineer.


I’m very passionate about language learning, both spoken languages and programming languages. I’m a native Chinese and Chengdu dialect speaker, and I started learning English from a very young age.

Hardware languages: Verilog, SystemVerilog, Assertions, UVM

Scripting languages: Python, Perl, Tcl, Ruby

Programming languages: C, C++, Assembly, Java


Since I was a young kid, my dream job has been to be an engineer. Now, here I am!
I work on ASIC design verification. My specialty is HDL (hardware description languages), including Verilog and SystemVerilog. Some of the projects I worked on before are covered in detail in the Project section. I also post regularly to share my thoughts related to design and verification topics in the Post section. I love coding and I cannot lie.
My mission is to apply what I’ve learned into the industry and work on products and technology that can change people’s lives.